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RTL8201CL RTL8201CL-lf RTL8201CL-vd RTL8201CL-vd-lf single-chip/single-port 10/100m fast ethernet phyceiver datasheet rev. 1.24 04 november 2005 track id: jatr-1076-21 realtek semiconductor corp. no. 2, innovation road ii, hsinchu science park, hsinchu 300, taiwan tel.: +886-3-578-0211. fax: +886-3-557-6047 www.realtek.com.tw www..net
RTL8201CL datasheet single-chip/port 10/100 fast ethernet ph yceiver ii track id: jatr-1076-21 rev. 1.24 copyright ?2005 realtek semiconductor corp. all rights reserv ed. no part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of realtek semiconductor corp. disclaimer realtek provides this document ?as is?, without wa rranty of any kind, neith er expressed nor implied, including, but not limited t o, the particular purpose. realtek may make improvements and/or changes in this document or in the product described in this document at any time. this document could include technical inaccuracies or typographical errors. trademarks realtek is a trademark of realtek semiconductor cor poration. other names mentioned in this document are trademarks/registered trademarks of their respective owners. using this document this document is intended for the software engin eer?s reference and provides detailed programming information. though every effort has been made to ensure that th is document is current and accurate, more information may have become available subsequent to the producti on of this guide. in that event, please contact your realtek representative for additional information that may help in the development process. www..net
RTL8201CL datasheet single-chip/port 10/100 fast ethernet ph yceiver iii track id: jatr-1076-21 rev. 1.24 revision history revision release date summary 1.0 2003/06/09 first release. 1.1 2003/09/26 minor cosmetic changes. modify led pin behavior. 1.2 2004/01/20 add led multi-mode definition (7.5 led and phy address configuration, page 19). add power dissipation info (table 31). bit <0:8> default setting changed to 0 (table 9). bit <0:13> default setting changed to 0 (table 9). bit <5:7> default setting changed to 0 (table 14). bit <17:5> default setting changed to 1 (table 17). bit <25:0> default setting changed to 0 (table 20). bit <25:1> default setting changed to 0 (table 20). bit <25:11~7> default setting changed to 00001 (table 20). 1.21 2004/10/12 package additions. see section 10, ordering information, page 33. 1.22 2005/04/11 correction to table 18, register 18 rx_er counter (rec), page 13. correction to table 39, transfor mer characteristics, page 30. added lead (pb)-free pack age identification information on page 3 and on page 33. 1.23 2005/07/29 corrected error in 7.8.3 10base-t tx/rx, page 21 (10base-t transmit function _ clock at 25mhz => clock at 2.5mhz). corrections to table 32, input voltage: vcc, page 23. vcc _ ttl voh _ minimum 0.9*vcc => minimum 0.65*vcc vcc _ ttl vol _ maximum 0.1*vcc => maximum 0.3*vcc vcc _ ttl ioz _ minimum -10ua => minimum -110ua vcc _ iin _ minimum -1.0ua => minimum -110ua vcc _ iin _ maximum 1.0ua => maximum 100ua 1.24 2005/11/04 revised table 1, page 4 (pins 2, 3, 4, 5, 6, and 25). corrected table 17, page 12 (bits 17:6 and 17:5). corrected table 18, page 13 (mode). revised table 32, page 23 (i in, i pl, i ph ). revised table 33, page 24 (t 8 ). revised table 34, page 25 (t 6, t 7, t 9 ). www..net
RTL8201CL datasheet single-chip/port 10/100 fast ethernet ph yceiver iv track id: jatr-1076-21 rev. 1.24 table of contents 1. general description............................................................................................................ ....................................1 2. features....................................................................................................................... ....................................................1 3. block diagram.................................................................................................................. ...........................................2 4. pin assignments ................................................................................................................ ...........................................3 4.1. l ead (p b )-f ree p ackage i dentification ................................................................................................................3 5. pin descriptions ............................................................................................................... ...........................................4 5.1. mii i nterface ............................................................................................................................... .............................4 5.2. sni (s erial n etwork i nterface ) 10m bps o nly ....................................................................................................5 5.3. c lock i nterface ............................................................................................................................... ........................5 5.4. 10m bps /100m bps n etwork i nterface ....................................................................................................................6 5.5. d evice c onfiguration i nterface ...........................................................................................................................6 5.6. led i nterface /phy a ddress c onfiguration .......................................................................................................6 5.7. p ower and g round p ins ............................................................................................................................... ...........7 5.8. r eset and o ther p ins ............................................................................................................................... ................7 6. register descriptions .......................................................................................................... ..................................8 6.1. r egister 0 b asic m ode c ontrol r egister ............................................................................................................8 6.2. r egister 1 b asic m ode s tatus r egister ...............................................................................................................9 6.3. r egister 2 phy i dentifier r egister 1....................................................................................................................9 6.4. r egister 3 phy i dentifier r egister 2....................................................................................................................9 6.5. r egister 4 a uto -n egotiation a dvertisement r egister (anar) ....................................................................10 6.6. r egister 5 a uto -n egotiation l ink p artner a bility r egister (anlpar)......................................................10 6.7. r egister 6 a uto -n egotiation e xpansion r egister (aner) .............................................................................11 6.8. r egister 16 nw ay s etup r egister (nsr).............................................................................................................12 6.9. r egister 17 l oopback , b ypass , r eceiver e rror m ask r egister (lbremr) .................................................12 6.10. r egister 18 rx_er c ounter (rec) .....................................................................................................................13 6.11. r egister 19 snr d isplay r egister .......................................................................................................................13 6.12. r egister 25 t est r egister ............................................................................................................................... ......13 7. functional description......................................................................................................... ..............................14 7.1. mii and m anagement i nterface ..........................................................................................................................14 7.1.1. data tran sitio n................................................................................................................ .....................................14 7.1.2. serial management.............................................................................................................. .................................15 7.2. a uto -n egotiation and p arallel d etection ......................................................................................................16 7.2.1. setting the medium type and interface mode to mac.............................................................................. ...........16 7.2.2. utp mode and mi i interface ..................................................................................................... ..........................16 7.2.3. utp mode and sn i interface ..................................................................................................... ..........................17 7.2.4. fiber mode and mii interface................................................................................................... ...........................17 7.3. f low c ontrol s upport ............................................................................................................................... ...........17 7.4. h ardware c onfiguration and a uto -n egotiation ............................................................................................18 7.5. led and phy a ddress c onfiguration ................................................................................................................19 7.6. s erial n etwork i nterface ............................................................................................................................... .....20 7.7. p ower d own , l ink d own , p ower s av i n g , and i solation m odes ......................................................................20 7.8. m edia i nterface ............................................................................................................................... ......................20 7.8.1. 100base-tx ..................................................................................................................... .....................................20 7.8.2. 100base-fx fiber mode operation................................................................................................ .....................21 7.8.3. 10base-t tx/rx ................................................................................................................. ..................................21 7.9. r epeater m ode o peration ............................................................................................................................... ......22 7.10. r eset , and t ransmit b ias ............................................................................................................................... .......22 www..net
RTL8201CL datasheet single-chip/port 10/100 fast ethernet ph yceiver v track id: jatr-1076-21 rev. 1.24 7.11. 3.3v p ower s upply and v oltage c onversion c ircuit .......................................................................................22 7.12. f ar e nd f ault i ndication ............................................................................................................................... .......22 8. characteristics ................................................................................................................ .......................................23 8.1. dc c haracteristics ............................................................................................................................... ................23 8.1.1. absolute maxi mum ratings ....................................................................................................... ...........................23 8.1.2. operating conditions ........................................................................................................... ................................23 8.1.3. power dissi pation .............................................................................................................. ..................................23 8.1.4. input volta ge: vcc ............................................................................................................. ...................................23 8.2. ac c haracteristics ............................................................................................................................... ................24 8.2.1. mii transmission cycle timing.................................................................................................. ..........................24 8.2.2. mii reception cycle ti ming ..................................................................................................... ............................25 8.2.3. sni transmission cycle timing.................................................................................................. ..........................27 8.2.4. sni reception c ycle ti ming ..................................................................................................... ............................28 8.2.5. mdc/mdio timing................................................................................................................ ..............................29 8.3. c rystal c haracteristics ............................................................................................................................... .......30 8.4. t ransformer c haracteristics ............................................................................................................................30 9. mechanical dimensions .......................................................................................................... .............................31 9.1. m echanical d imensions n otes ............................................................................................................................32 10. ordering information........................................................................................................... ...........................33 list of tables table 1. mii interface....................................................................................................... ...........................4 table 2. sni (serial network interface) 10mbps only .......................................................................... ....5 table 3. clock interface ..................................................................................................... .........................5 table 4. 10mbps/100mbps network interface.................................................................................... ........6 table 5. device configuration interface ...................................................................................... ...............6 table 6. led interface/phy address configuration............................................................................. .....7 table 7. power and ground pins ............................................................................................... ..................7 table 8. reset and other pins................................................................................................ ......................7 table 9. register 0 basic mode control register .............................................................................. .........8 table 10. register 1 basic mode status register................................................................................ ..........9 table 11. register 2 phy identifier register 1................................................................................. ............9 table 12. register 3 phy identifier register 2................................................................................. ............9 table 13. register 4 auto-negotiation advertisement register (anar)..................................................10 table 14. register 5 auto-negotiation link partner ability register (anlpar) ....................................10 table 15. register 6 auto-negotiati on expansion register (aner) .........................................................11 table 16. register 16 nway setup register (nsr)................................................................................ ....12 table 17. register 17 loopback, bypass, receiver error mask register (lbremr) ..............................12 table 18. register 18 rx_er counter (rec)...................................................................................... ......13 table 19. register 19 snr display register ..................................................................................... .........13 table 20. register 25 test register............................................................................................ .................13 table 21. serial management .................................................................................................... ..................15 table 22. setting the medium type and interface mode to mac..............................................................16 www..net
RTL8201CL datasheet single-chip/port 10/100 fast ethernet ph yceiver vi track id: jatr-1076-21 rev. 1.24 table 23. utp mode and mii interface ........................................................................................... ...........16 table 24. utp mode and sni interface........................................................................................... ...........17 table 25. fiber mode and mii interface ......................................................................................... ............17 table 26. auto-negotiation mode pin settings ................................................................................... .......18 table 27. led definitions ...................................................................................................... ....................19 table 28. power saving mode pin settings ....................................................................................... .........20 table 29. absolute maximum ratings............................................................................................. ...........23 table 30. operating conditions................................................................................................. ..................23 table 31. power dissipation.................................................................................................... ....................23 table 32. input voltage: vcc................................................................................................... ....................23 table 33. mii transmission cycle timing ........................................................................................ .........24 table 34. mii reception cycle timing........................................................................................... ............25 table 35. sni transmission cycle timing ........................................................................................ .........27 table 36. sni reception cycle timing ........................................................................................... ...........28 table 37. mdc/mdio timing...................................................................................................... ..............29 table 38. crystal characteristics.............................................................................................. ...................30 table 39. transformer characteristics .......................................................................................... ..............30 table 40. ordering information................................................................................................. ..................33 list of figures figure 1. block diagram ...................................................................................................... .......................2 figure 2. pin assignments.................................................................................................... .......................3 figure 3. read cycle ......................................................................................................... ........................15 figure 4. write cycle ........................................................................................................ ........................15 figure 5. led and phy address configuration.................................................................................. .....19 figure 6. mii transm ission cycle timing-1.................................................................................... .........24 figure 7. mii transm ission cycle timing-2.................................................................................... .........25 figure 8. mii reception cycle timing-1 ....................................................................................... ...........26 figure 9. mii reception cycle timing-2 ....................................................................................... ...........26 figure 10. sni transmission cycle timing-1 ..................................................................................... .......27 figure 11. sni transmission cycle timing-2 ..................................................................................... .......27 figure 12. sni reception cycle timing-1........................................................................................ ..........28 figure 13. sni reception cycle timing-2........................................................................................ ..........28 figure 14. mdc/mdio timing ..................................................................................................... .............29 figure 15. mdc/mdio mac to phy tr ansmission without collision ...................................................29 figure 16. mdc/mdio phy to mac reception without error ...............................................................30 www..net
RTL8201CL datasheet single-chip/port 10/100 fast ethernet ph yceiver 1 track id: jatr-1076-21 rev. 1.24 1. general description the RTL8201CL is a single-chip/si ngle-port phyceiver with an mii (m edia independent interface)/sni (serial network interface). it implements all 10/100m ethernet p hysical-layer functions including the physical coding sublayer (pcs), physical medium attachment (pma), twiste d pair physical medium dependent sublayer (tp-pmd), 10base-tx encoder/ decoder, and twisted-pair media access unit (tpmau). a pecl (pseudo emitter coupled logic) interface is supported to connect with an external 100base-fx fiber optical transceiver. the chip utilizes an advanced cmos pro cess to meet low voltage and low power requirements. with on-chip dsp (digital signal processing ) technology, the chip provides excellent performance under all operating conditions. the RTL8201CL can be used for applications such as those for a network interface adapter, mau (media access unit), cnr (communication and network riser), acr (advanced communication riser), an ethernet hub, and an ethernet switch. in addition, it can be used in any embedded system with an ethernet mac that needs a utp physical conn ection or fiber pecl in terface to an external 100base-fx optical transceiver module. 2. features the realtek RTL8201CL is a fast ethernet phyceiver with selectable mii or sni interface to the mac chip. it provides th e following features: ? pin-to-pin compatible with the rtl8201bl ? supports mii and 7-wire sni (serial network interface) ? 10/100mbps operation ? full/half duplex operation ? twisted pair or fiber mode output ? auto-negotiation ? supports power down mode ? supports operation under link down power saving mode ? supports base line wander (blw) compensation ? supports repeater mode ? adaptive equalization ? network status leds ? flow control support ? 25mhz crystal/oscillator as clock source ? ieee 802.3/802.3u compliant ? supports ieee 802.3u clause 28; 1.8v operation with 3.3v io signal tolerance ? low dual power supply, 1.8v and 3.3v; 1.8v is generated by an internal regulator ? 0.18m cmos process ? 48-pin lqfp package www..net
RTL8201CL datasheet single-chip/port 10/100 fast ethernet ph yceiver 2 track id: jatr-1076-21 rev. 1.24 3. block diagram figure 1. block diagram rxin+ rxin- txo+ txo - rxc 25m 25m txc 25m txd rxd td+ variable current 3 level driver master ppl adaptive equalizer peak detect 3 level comparator control voltage mlt-3 to nrzi serial to parrallel ck data slave pll parrallel to serial baseline wander correction 5b 4b decoder data alignment descrambler 4b 5b encoder scrambler 10/100 half/full switch logic 10/100m auto-negotiation control logic manchester coded waveform 10m output waveform shaping data recovery receive low pass filter rxd rxc 25m txd txc 25m txd10 txc10 rxd10 rxc10 link pulse 10m 100m mii interface sni interface www..net
RTL8201CL datasheet single-chip/port 10/100 fast ethernet ph yceiver 3 track id: jatr-1076-21 rev. 1.24 4. pin assignments 7. txc 2. txen 3. txd3 4. txd2 5. txd1 6. txd0 16. rxc 1. col 23. crs 22. rxdv 18. rxd3 19. rxd2 20. rxd1 21. rxd0 25. mdc 26. mdio 46. x1 47. x2 33. tptx- 34. tptx+ 28. rtset 31. tprx+ 30. tprx- 43. isolate 40. rptr 39. speed 38. duplex 37. ane 41. ldps 44. mii/snib 9. led0/ phyad0 10. led1/ 12. led2/ phyad2 13. led3/ phyad3 15. led4/ phyad4 27. nc 42. resetb 48. dvdd33 32. pwfbout 36. avdd33 29. agnd 35. agnd 45. dgnd 8. pwfbin 14. dvdd33 17. dgnd 11. dgnd phyad1 24. rxer /fxen RTL8201CL lllllll txxxx taiwan figure 2. pin assignments 4.1. lead (pb)-free package identification lead (pb)-free package is indicated by an ?l? in the location marked ?t? in figure 2. www..net
RTL8201CL datasheet single-chip/port 10/100 fast ethernet ph yceiver 4 track id: jatr-1076-21 rev. 1.24 5. pin descriptions li: latched input during power up or reset o: output i: input io: bi-directional input and output p: power 5.1. mii interface table 1. mii interface name type pin no. description txc o 7 transmit clock. this pin provides a continuous clock as a timing reference for txd[3:0] and txen. txen i 2 transmit enable. the input signal indicates the presence of valid nibble data on txd[3:0]. an internal weak pull low resistor prevents the bus floating. txd[3:0] i 3, 4, 5, 6 transmit data. the mac will source txd[0..3] synchr onous with txc when txen is asserted. an internal weak pull high resistor prevents the bus floating. rxc o 16 receive clock. this pin provides a continuous clock reference for rxdv and rxd[0..3] signals. rxc is 25mhz in 100mbps mode and 2.5mhz in 10mbps mode. col li/o 1 collision detect. col is asserted high when a collision is detected on the media. during power on reset, this pin status is latched to determine at which led mode to operate: 0: cl led mode 1: bl led mode an internal weak pull low resistor sets this to the default cl led mode. it is possible to use an external 5.1k ? pull high resistor to enable bl led mode. crs li/o 23 carrier sense. this pin?s signal is asserted high if the media is not in idle state. an internal weak pull low resistor sets this to normal operation mode. an external 5.1k ? pull low resistor could be reserved to ensure operating at normal mode. rxdv o 22 receive data valid. this pin?s signal is asserted high when received data is present on the rxd[3:0] lines. the signal is de-asserted at the end of the pack et. the signal is valid on the rising edge of the rxc. rxd[3:0] o 18, 19, 20, 21 receive data. these are the four parallel receive data lines aligned on the nibble boundaries driven synchronously to the rxc for r eception by the external physical unit (phy). www..net
RTL8201CL datasheet single-chip/port 10/100 fast ethernet ph yceiver 5 track id: jatr-1076-21 rev. 1.24 name type pin no. description rxer/ fxen o/li 24 receive error. if a 5b decode error occurs, such as invalid /j/k/, invalid /t/r/, or invalid symbol, this pin will go high. fiber/utp enable. during power on reset, this pin status is latched to determine the media mode to operate in. 1: fiber mode 0: utp mode an internal weak pull low resistor sets this to the default of utp mode. it is possible to use an external 5.1k ? pull high resistor to enable fiber mode. after power on, the pin operates as the receive error pin. mdc i 25 management data clock. this pin provides a clock synchronous to mdio, which may be asynchronous to the transmit txc and receive rxc clocks. the clock rate can be up to 2.5mhz. an internal weak pull high resistor prevents the bus floating. mdio io 26 management data input/output. this pin provides the bi-directional signal used to transfer management information. 5.2. sni (serial network interface) 10mbps only table 2. sni (serial network interface) 10mbps only name type pin no. description col o 1 collision detect. rxd0 o 21 received serial data. crs o 23 carrier sense. rxc o 16 receive clock. resolved from received data. txd0 i 6 transmit serial data. txc o 7 transmit clock. generated by phy. txen i 2 transmit enable. for mac to indicate transmit operation. 5.3. clock interface table 3. clock interface name type pin no. description x2 o 47 25mhz crystal output. this pin provides the 25mhz crystal output. it must be left open when an external 25mhz oscillator drives x1. x1 i 46 25mhz crystal input. this pin provides the 25mhz crystal input. if a 25mhz oscillator is used, connect x1 to the oscillator?s output (see 8.3 crystal characteristics, page 30, for clock source specifications. www..net
RTL8201CL datasheet single-chip/port 10/100 fast ethernet ph yceiver 6 track id: jatr-1076-21 rev. 1.24 5.4. 10mbps/100mbps network interface table 4. 10mbps/100mbps network interface name type pin no. description tptx+ tptx- o o 34 33 transmit output. differential transmit output pair shared by 100base-tx, 100base-fx and 10base-t modes. when configured as 100base-tx, output is an mlt-3 encoded waveform. when configured as 100base-fx, the output is pseudo-ecl level. rtset i 28 transmit bias resistor connection. this pin should be pulled to gnd by a 2k ? (1%) resistor to define driving current for the transmit dac. the resistan ce value may be changed, depending on experimental results of the RTL8201CL. tprx+ tprx- i i 31 30 receive input. differential receive input pair shar ed by 100base-tx, 100base-fx, and 10base-t modes. 5.5. device configuration interface table 5. device configuration interface name type pin no. description isolate i 43 set high to isolate the RTL8201CL from the mac. this will also isolate the mdc/mdio management interface. in this mode, the power consumption is minimum. this pin can be directly connected to gnd or vcc. rptr i 40 set high to put the RTL8201CL into repeater mode. this pin can be directly connected to gnd or vcc. speed li 39 this pin is latched to input during a power on or reset condition. set high to put the RTL8201CL into 100mbps operation. this pin can be directly connected to gnd or vcc. duplex li 38 this pin is latched to input during a power on or reset condition. set high to enable full duplex. this pin can be directly connected to gnd or vcc. ane li 37 this pin is latched to input during a power on or reset condition. set high to enable auto-negotiation mode, set low to force mode. this pin can be directly connected to gnd or vcc. ldps i 41 set high to put the RTL8201CL into ldps mode. this pin can be directly connected to gnd or vcc. see 7.7 power down, link down, power saving, and isolation modes, page 20, for more information. mii/snib li/o 44 this pin is latched to input during a power on or reset condition. pull high to set the RTL8201CL into mii mode operation. set low for sni mode. this pin can be directly connected to gnd or vcc. 5.6. led interface/phy address configuration these five pins are latched into the RTL8201CL dur ing power up reset to configure the phy address [0:4] used for the mii management re gister interface. in normal operation, af ter initial reset, they are used as driving pins for status indicator leds. the drivi ng polarity, active low or activ e high, is determined by each latched status of the phy address [4:0] during pow er-up reset. if the latched status is high, then it will be active low. if the latched status is low, then it will be act ive high. see section 7.5 led and phy address configuration, page 19, for more information. www..net
RTL8201CL datasheet single-chip/port 10/100 fast ethernet ph yceiver 7 track id: jatr-1076-21 rev. 1.24 table 6. led interface/phy address configuration name type pin no. description phyad0/ led0 li/o 9 phy address [0]. link led. lit when linked. phyad1/ led1 li/o 10 phy address [1]. full duplex led. lit when in full duplex operation. phyad2/ led2 li/o 12 phy address [2]. cl led mode: 10 act led blinking when transmitting or receiving data. bl led mode: link 10 / act led active when linked in 10base-t mode, and blinking when transmitting or receiving data. phyad3/ led3 li/o 13 phy address [3]. cl led mode: 100 act led blinking when transmitting or receiving data. bl led mode: link 100 / act led active when linked in 100base-t mode, and blinking when transmitting or receiving data. phyad4/ led4 li/o 15 phy address [4]. collision led. blinks when collisions occur. 5.7. power and ground pins table 7. power and ground pins name type pin no. description avdd33 p 36 3.3v analog power input. 3.3v power supply for analog circuit; should be well decoupled. agnd p 29, 35 analog ground. should be connected to a larger gnd plane. dvdd33 p 14, 48 3.3v digital power input. 3.3v power supply for digital circuit. dgnd p 11, 17, 45 digital ground. should be connected to a larger gnd plane. 5.8. reset and other pins table 8. reset and other pins name type pin no. description resetb i 42 resetb. set low to reset the chip. for a complete reset, this pin must be asserted low for at least 10ms. pwfbout o 32 power feedback output. be sure to connect a 22uf tantalum capacitor for frequency compensation and a 0.1uf capacitor for noise de-coupling. then connect this pin through a ferrite bead to pwfbin (pin8). the co nnection method is outlined in section 7.11 3.3v power supply and voltage conversion circuit, page 22. pwfbin i 8 power feedback input. see the pwfbout description above. nc 27 not connected. www..net
RTL8201CL datasheet single-chip/port 10/100 fast ethernet ph yceiver 8 track id: jatr-1076-21 rev. 1.24 6. register descriptions this section describes the func tions and usage of the register s available in the RTL8201CL. in this section the following abbreviations are used: ro: read only rw: read/write 6.1. register 0 basic mode control register table 9. register 0 basic mode control register address name description mode default 0:15 reset this bit sets the status and control registers of the phy in a default state. this bit is self-clearing. 1: software reset 0: normal operation rw 0 0:14 loopback this bit enables loopback of transmit data nibbles txd3:0 to the receive data path. 1: enable loopback 0: normal operation rw 0 0:13 spd_set this bit sets the network speed. 1: 100mbps 0: 10mbps after completing auto negotiation, this bit will reflect the speed status. 1: 100base-t 0: 10base-t) when 100base-fx mode is enabled, this bit=1 and is read only. rw 0 0:12 auto negotiation enable this bit enables/disables the nway auto-negotiation function. 1: enable auto-negotiation; bits 0:13 and 0:8 will be ignored. 0: disable auto-negotiation; bits 0:13 and 0:8 will determine the link speed and the data transfer mode, respectively. when 100base-fx mode is enabled, this bit=0 and is read only. rw 1 0:11 power down this bit turns down the power of the phy chip, including the internal crystal oscillator circu it. the mdc, mdio is still alive for accessing the mac. 1: power down 0: normal operation rw 0 0:10 reserved 0:9 restart auto negotiation this bits allows the nway auto-negotiation function to be reset. 1: re-start auto-negotiation 0: normal operation rw 0 0:8 duplex mode this bit sets the duplex mode if auto-negotiation is disabled (bit 0:12=0). 1: full duplex 0: half duplex after completing auto-negotiation, this bit will reflect the duplex status. 1: full duplex 0: half duplex rw 0 0:7:0 reserved www..net
RTL8201CL datasheet single-chip/port 10/100 fast ethernet ph yceiver 9 track id: jatr-1076-21 rev. 1.24 6.2. register 1 basic mode status register table 10. register 1 basic mode status register address name description mode default 1:15 100base-t4 1: enable 100base-t4 support 0: suppress 100base-t4 support ro 0 1:14 100base_tx_ fd 1: enable 100base-tx full duplex support 0: suppress 100base-tx full duplex support ro 1 1:13 100base_tx_hd 1: enable 100base-tx half duplex support 0: suppress 100base-tx half duplex support ro 1 1:12 10base_t_fd 1: enable 10base-t full duplex support 0: suppress 10base-t full duplex support ro 1 1:11 10_base_t_hd 1: enable 10base-t half duplex support 0: suppress 10base-t half duplex support ro 1 1:10~7 reserved 1:6 mf preamble suppression the RTL8201CL will accept ma nagement frames with preamble suppressed. a minimum of 32 preamble bits are required for the first smi read/write transaction after rese t. one idle bit is required between any two management transactions as per ieee 802.3u specifications. ro 1 1:5 auto negotiation complete 1: auto-negotiation process completed 0: auto-negotiation process not completed ro 0 1:4 remote fault 1: remote fault condition detected (cleared on read) 0: no remote fault condition detected when in 100base-fx mode, this bit means an in- b and signal far-end-fault has been detected. see 0 far end fault indication, page 22. ro 0 1:3 auto negotiation 1: link has not experienced fail state 0: link experienced fail state ro 1 1:2 link status 1: valid link established 0: no valid link established ro 0 1:1 jabber detect 1: jabber condition detected 0: no jabber condition detected ro 0 1:0 extended capability 1: extended register capability 0: basic register capability only ro 1 6.3. register 2 phy identifier register 1 table 11. register 2 phy identifier register 1 address name description mode default 2:15~0 phyid1 phy identifier id for software recognition of the RTL8201CL ro 0000 6.4. register 3 phy identifier register 2 table 12. register 3 phy identifier register 2 address name description mode default 3:15~0 phyid2 phy identifier id for softwa re recognition of the RTL8201CL ro 8201 www..net
RTL8201CL datasheet single-chip/port 10/100 fast ethernet ph yceiver 10 track id: jatr-1076-21 rev. 1.24 6.5. register 4 auto-negotiation advertisement register (anar) this register contains the advertised abilities of this device as they wi ll be transmitted to its link partner during auto-negotiation. table 13. register 4 auto-negotiation advertisement register (anar) address name description mode default 4:15 np next page bit. 0: transmitting the primary capability data page 1: transmitting the protocol specific data page ro 0 4:14 ack 1: acknowledge reception of link partner capability data word 0: do not acknowledge reception ro 0 4:13 rf 1: advertise remote fault detection capability 0: do not advertise remote fault detection capability rw 0 4:12 reserved 4:11 txfc 1: tx flow control is supported by local node 0: tx flow control not supported by local node rw 0 4:10 rxfc 1: rx flow control is supported by local node 0: rx flow control not supported by local node rw 0 4:9 t4 1: 100base-t4 is supported by local node 0: 100base-t4 not supported by local node ro 0 4:8 txfd 1: 100base-tx full duplex is supported by local node 0: 100base-tx full duplex not supported by local node rw 1 4:7 tx 1: 100base-tx is supported by local node 0: 100base-tx not supported by local node rw 1 4:6 10fd 1: 10base-t full duplex supported by local node 0: 10base-t full duplex not supported by local node rw 1 4:5 10 1: 10base-t is supported by local node 0: 10base-t not supported by local node rw 1 4:4~0 selector binary encoded selector supported by this node. currently only csma/cd 00001 is specified. no other protocols are supported. rw 00001 6.6. register 5 auto-negotiation link partner ability register (anlpar) this register contains the advertised abilities of th e link partner as received dur ing auto-negotiation. the content changes after a successful auto-n egotiation if next-p ages are supported. table 14. register 5 auto -negotiation link partner ability register (anlpar) address name description mode default 5:15 np next page bit. 0: transmitting the primary capability data page 1: transmitting the protocol specific data page ro 0 5:14 ack 1: link partner acknowledges reception of local node?s capability data word 0: no acknowledgement ro 0 5:13 rf 1: link partner is indicating a remote fault 0: link partner does not indicate a remote fault ro 0 5:12 reserved 5:11 txfc 1: tx flow control is supported by link partner 0: tx flow control not supported by link partner ro 0 www..net
RTL8201CL datasheet single-chip/port 10/100 fast ethernet ph yceiver 11 track id: jatr-1076-21 rev. 1.24 address name description mode default 5:10 rxfc 1: rx flow control is supported by link partner 0: rx flow control not supported by link partner ro 0 5:9 t4 1: 100base-t4 is supported by link partner 0: 100base-t4 not supported by link partner ro 0 5:8 txfd 1: 100base-tx full duplex is supported by link partner 0: 100base-tx full duplex not supported by link partner ro 0 5:7 100base-tx 1: 100base-tx is supported by link partner 0: 100base-tx not supported by link partner this bit will also be set if the link in 100base is established by parallel detection. ro 0 5:6 10fd 1: 10base-t full duplex is supported by link partner 0: 10base-t full duplex not supported by link partner ro 0 5:5 10base-t 1: 10base-t is supported by link partner 0: 10base-t not supported by link partner this bit will also be set if the link in 10base-t is established by parallel detection. ro 0 5:4~0 selector link partner?s binary encoded node selector currently only csma/cd 00001 is specified ro 00000 6.7. register 6 auto-negotiation expansion register (aner) this register contains additional status for nway auto-negotiation. table 15. register 6 auto-negotiation expansion register (aner) address name description mode default 6:15~5 reserved this bit is permanently set to 0. 6:4 mlf indicates whether a multiple link fault has occurred. 1: fault occurred 0: no fault occurred ro 0 6:3 lp_np_able indicates whether the link partner supports next page negotiation. 1: supported 0: not supported ro 0 6:2 np_able this bit indicates whether the local node is able to send additional next pages. internal use only. ro 0 6:1 page_rx this bit is set when a new link code word page has been received. it is automatically cl eared when the auto-negotiation link partner?s ability register (register 5) is read by management. ro 0 6:0 lp_nw_able 1: link partner supports nway auto-negotiation. ro 0 www..net
RTL8201CL datasheet single-chip/port 10/100 fast ethernet ph yceiver 12 track id: jatr-1076-21 rev. 1.24 6.8. register 16 nway setup register (nsr) table 16. register 16 nway setup register (nsr) address name description mode default 16:15~12 reserved 16:11 ennwle 1: led4 pin indicates linkpulse rw 0 16:10 testfun 1: auto-negotiation speeds up internal timer rw 0 16:9 nwlpbk 1: set nway to loopback mode rw 0 16:8~3 reserved 16:2 flagabd 1: auto-negotiation experienced ability detect state ro 0 16:1 flagpdf 1: auto-negotiation experienced parallel detection fault state ro 0 16:0 flaglsc 1: auto-negotiation experienced link status check state ro 0 6.9. register 17 loopback, bypass, receiver error mask register (lbremr) table 17. register 17 loopback, bypass, receiver error mask register (lbremr) address name description mode default 17:15 rptr set to 1 to put the RTL8201CL into repeater mode. rw 0 17:14 bp_4b5b assertion of this bit allows bypassing of the 4b/5b & 5b/4b encoder. rw 0 17:13 bp_scr assertion of this bit allows bypassing of the scrambler/descrambler. rw 0 17:12 ldps set to 1 to enable link down power saving mode. rw 0 17:11 analogoff set to 1 to power down analog function of transmitter and receiver. rw 0 17:10 reserve reserved. 17:9 lb set to 1 to enable dsp loopback. rw 0 17:8 f_link_10 used to logic force good link in 10mbps for diagnostic purposes. rw 1 17:7 f_link_100 used to logic force good link in 100mbps for diagnostic purposes. rw 1 17:6 jben set to 1 to enable jabber function in 10base-t. rw 1 17:5 code_err assertion of this bit causes a code error detection to be reported. rw 0 17:4 pme_err assertion of this bit causes a pre-mature end error detection to be reported. rw 0 17:3 link_err assertion of this bit causes a link error detection to be reported. rw 0 17:2 pkt_err assertion of this bit causes a ?detection of pack et errors due to 722 ms time-out? to be reported. rw 0 17:1 fxmode this bit indicates whether fiber mode is enabled. ro 0 17:0 rmiimode this bit indicates whether rmii mode is enabled. ro 0 www..net
RTL8201CL datasheet single-chip/port 10/100 fast ethernet ph yceiver 13 track id: jatr-1076-21 rev. 1.24 6.10. register 18 rx_er counter (rec) table 18. register 18 rx_er counter (rec) address name description mode default 18:15~0 rxercnt this 16-bit counter increments by 1 for each invalid packet received. the value is valid while a link is established. ro h?[0000] 6.11. register 19 snr display register table 19. register 19 snr display register address name description mode default 19:15~4 reserved realtek test mode internal use. do not change this field without realtek?s approval. 19:3~0 snr these 4-bits show the signal to noise ratio value. rw 0000 6.12. register 25 test register table 20. register 25 test register address name description mode default 25:15~12 test reserved for internal testing. rw 25:11~7 phyad[4:0] reflects the phy address defined by external phy address configuration pins. ro 00001 25:6~2 test reserved for internal testing. ro 25:1 link10 1: 10base-t link established 0: no 10base-t link established ro 0 25:0 link100 1: 100base-fx or 100base-tx link established 0: no 100base link established ro 0 www..net
RTL8201CL datasheet single-chip/port 10/100 fast ethernet ph yceiver 14 track id: jatr-1076-21 rev. 1.24 7. functional description the RTL8201CL phyceiver is a physical la yer device that integrates 10base-t and 100base-tx/100base-fx functions, and some extra power management features into a 48-pin single chip that is used in 10/100 fast ethe rnet applications. this device supports the following functions: ? mii interface with mdc/md io smi management interface to communicate with mac ? ieee 802.3u clause 28 auto-negotiation ability ? flow control ability suppor t to cooperate with mac ? speed, duplex, auto-negotiati on ability configurable by hard wire or mdc/mdio ? flexible led configuration ? 7-wire sni (serial network interf ace) support (only in 10mbps mode) ? power down mode support ? 4b/5b transform ? scrambling/de-scrambling ? nrz to nrzi, nrzi to mlt-3 ? manchester encode and d ecode for 10base-t operation ? clock and data recovery ? adaptive equalization ? far end fault indication (fefi) in fiber mode 7.1. mii and management interface 7.1.1. data transition to set the RTL8201CL for mii mode operation, pu ll the mii/snib pin high and set the ane, speed, and duplex pins. the mii (media independent interf ace) is an 18-signal interface (as described in ieee 802.3u) supplying a standard interface between the phy and mac layer. this interface operates at two frequencies ? 25mhz and 2.5mhz to support 100mbps/10mbps bandwid th for both transmit and receive functions. transmission the mac asserts the txen signal. it then changes byt e data into 4-bit nibbles and passes them to the phy via txd[0..3]. the phy will sample txd[0..3 ] synchronously with txc ? the transmit clock signal supplied by phy ? during the interval txen is asserted. reception the phy asserts the rxen signal. it passes the r eceived nibble data rxd[ 0..3] clocked by rxc. crs and col signals are used for co llision detection and handling. in 100base-tx mode, when the decode d signal in 5b is not idle, the crs signal will assert. when 5b is recognized as idle it will be de-asserted. in 10bas e-t mode, crs will assert when the 10m preamble has been confirmed and will be de-asserted when the idle pattern has been confirmed. www..net
RTL8201CL datasheet single-chip/port 10/100 fast ethernet ph yceiver 15 track id: jatr-1076-21 rev. 1.24 the rxdv signal will be asserted when decoded 5b are /j/k/ and will be de-asserted if the 5b are /t/r/ or idle in 100mbps mode. in 10mbps mode, the rxdv signal is the same as the crs signal. the rxer (receive error) sign al will be asserted if any 5b decode errors occur such as invalid j/k, invalid t/r, or invalid symbol. this pin will go high for one or more clock periods to indicate to the reconciliation sublayer that an error was detected somewhere in the frame. note: the RTL8201CL does not use a txer signal. this does not affect the transmit function. 7.1.2. serial management the mac layer device can use the mdc/mdio mana gement interface to control a maximum of 31 RTL8201CL devices, configured with different p hy addresses (00001b to 11111b). during a hardware reset, the logic levels of pins 9, 10, 12, 13, 15 are latched into the RTL8201CL to be set as the phy address for management communication via the serial interface. setting the p hy address to 00000b will put the RTL8201CL into power down mode. the read and write frame structure for the management interface is illu strated in figure 3 and figure 4. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a4 a3 a2 a1 a0 r4 r3 r2 r1 r0 0 1 1 0 0 32 1s op st preamble phyad[4:0] ta data regad[4:0] idle mdc mdio mdio is sourced by mac. clock data into phy on rising edge of mdc z mdio is sourced by phy. clock data from phy on rising edge of mdc figure 3. read cycle d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a4 a3 a2 a1 a0 r4 r3 r2 r1 r0 1 0 1 0 1 0 32 1s op st preamble phyad[4:0] ta data regad[4:0] idle mdc mdio mdio is sourced by mac. clock data into phy on rising edge of mdc figure 4. write cycle table 21. serial management name description preamble 32 contiguous logical ?1?s sent by the mac on mdio along with 32 corresponding cycles on mdc. this provides synchronization for the phy. st start of frame. indicated by a 01 pattern. op operation code. read: 10 write: 01 phyad phy address. up to 31 phys can be connected to one mac. this 5-bit fi eld selects which phy the frame is directed to. regad register address. this is a 5-bit field that sets which of the 32 registers of the phy this operation refers to. ta turnaround. this is a 2-bit time- spacing between the register address and the data field of a frame to avoid contention during a read transaction. for a read transaction, both the sta and the phy shall remain in a high-impedance state for the first bit time of the turnaround. the phy shall drive a zero bit during the second bit time of the turnaround of a read transaction. data data. these are the 16 bits of data. idle idle condition. not truly part of the management frame. this is a high impedance state. electrically, the phy?s pull-up resistor will pull the mdio line to a logical ?1?. www..net
RTL8201CL datasheet single-chip/port 10/100 fast ethernet ph yceiver 16 track id: jatr-1076-21 rev. 1.24 7.2. auto-negotiation and parallel detection the RTL8201CL supports ieee 802.3u clause 28 auto-neg otiation for operation with other transceivers supporting auto-negotiation. the RTL8201CL can auto de tect the link partner?s abilities and determine the highest speed/duplex configurat ion possible between the two device s. if the link partner does not support auto-negotiation, then the RTL8201CL will enable half duplex mode and enter parallel detection mode. the RTL8201CL will default to transmit flp (f ast link pulse) and wait for the link partner to respond. if the RTL8201CL receives fl p, then the auto-negotiation pr ocess will go on. if it receives nlp (normal link pulse), then the RTL8201CL will change to 10mbps and half duplex mode. if it receives a 100mbps idle pattern, it will change to 100mbps and half duplex mode. to enable auto-negotiation mode operation on the RTL8201CL, pull the ane (auto-negotiation enable) pin high. the speed and duplex pins will set the ab ility content of the auto-negotiation register. auto-negotiation mode can be externally disabled by pulling the ane pin low. in this case, the speed pin and duplex pin will change the me dia configuration of the RTL8201CL. below is a list of all configurations of the an e/speed/duplex pins and their operation in fiber or utp mode. 7.2.1. setting the medium type a nd interface mode to mac table 22. setting the medium type and interface mode to mac fx (pin 24) mii/snib (pin 44) operation mode l h utp mode and mii interface. l l utp mode and sni interface. h x fiber mode and mii interface. 7.2.2. utp mode and mii interface table 23. utp mode and mii interface ane (pin 37) speed (pin 39) duplex (pin 38) operation h l l auto-negotiation enabled. the ability field does not support 100mbps or full duplex mode operation. h l h auto-negotiation enabled. the ability field does not support 100mbps operation. h h l auto-negotiation enabled. the ability field does not support full duplex mode operation. h h h default setup, auto-negotiation enabled. the RTL8201CL supports 10base- t /100base-tx, half/full duplex mode operation. l l l auto-negotiation disabled. forces the RTL8201CL into 10base-t and half duplex mode. l l h auto-negotiation disabled. forces the RTL8201CL into 10base-t and full duplex mode. l h l auto-negotiation disabled. forces the RTL8201CL into 100base-tx and half duplex mode. l h h auto-negotiation disabled. forces the RTL8201CL into 100base-tx and full duplex mode. www..net
RTL8201CL datasheet single-chip/port 10/100 fast ethernet ph yceiver 17 track id: jatr-1076-21 rev. 1.24 7.2.3. utp mode and sni interface sni interface to mac (only ope rates in 10base-t when the sni interface is enabled) table 24. utp mode and sni interface ane (pin 37) speed (pin 39) duplex (pin 38) operation x x l the duplex pin is pulled low to support the 10base-t half duplex function. 10base-t half duplex is the specified default mode in the sni interface. x x h the RTL8201CL also supports full duplex in sni mode. the duplex pin is pulled high to support 10base-t full duplex function. 7.2.4. fiber mode and mii interface the RTL8201CL only supports 100base-fx when fiber mode is enabled. ane (auto-negotiation enable) and speed configuration is i gnored when fiber mode is enabled. table 25. fiber mode and mii interface ane (pin 37) speed (pin 39) duplex (pin 38) operation x x h the duplex pin is pulled high to support 100base-fx full duplex function. x x l the duplex pin is pulled low to support 100base-fx half duplex function. 7.3. flow control support the RTL8201CL supports flow control indications. the mac can program the mii re gister to indicate to the phy that flow control is supported. when the mac supports the flow control mechanism, setting bit 10 of the anar register using the mdc/mdio smi interface, then the RTL8201CL will add the ability to its nway ability. if th e link partner also supports flow control, then the RTL8201CL can recognize the link partner?s nway ability by examining bit 10 of anlpar (register 5). www..net
RTL8201CL datasheet single-chip/port 10/100 fast ethernet ph yceiver 18 track id: jatr-1076-21 rev. 1.24 7.4. hardware configuration and auto-negotiation this section describes methods to configure the RTL8201CL and set the auto-negotiation mode. table 26 shows the various pins and their settings. table 26. auto-negotiation mode pin settings pin name description isolate set high to isolate the RTL8201CL from the mac. this will also isolate the mdc/mdio management interface. in this mode, power cons umption is minimum (see 7.7 power down, link down, power saving, and isolation modes, page 20). rptr pull high to set the RTL8201CL into repeat er mode. this pin is pulled low by default (see 7.9 repeater mode operation, page 22. ldps pull high to set the RTL8201CL into ldps mode. this pin is pulled low by default (see 7.7 power down, link down, power saving, and isolation modes, page 20). mii/snib pull high to set RTL8201CL into mii mode operation, which is the default mode for the rtl8201. this pin pulled low will set the RTL8201CL into sni mode operation. when set to sni mode, the RTL8201CL will operate at 10mbps (see 7. 6 serial network interface, page 20). ane auto-negotiation enable. pull high to enable au to-negotiation (default). pull low to disable auto- negotiation and activate the parallel detection mechanism (see 7.2 auto-negotiation and parallel detection, page 16). speed when ane is pulled high, the ability to adjust sp eed is setup. when ane is pulled low, pull this pin low to force 10mbps operation and high to force 100mbps operation (see 7.2 auto-negotiation and parallel detection, page 16). duplex when ane is pulled high, the ability to adjust the duplex pin will be se tup. when ane is pulled low, pull this pin low to force half duplex and high to force full duplex operation (see 7.2 auto- negotiation and parallel detection, page 16). www..net
RTL8201CL datasheet single-chip/port 10/100 fast ethernet ph yceiver 19 track id: jatr-1076-21 rev. 1.24 7.5. led and phy address configuration in order to reduce the pin count on the RTL8201CL, the led pins are duplexed with the phy address pins. because the phyad strap options share the led output pins, the external combinations required for strapping and led usage must be considered in order to avoid contention. specifically, when the led outputs are used to drive leds direc tly, the active state of each output driver is dependent on the logic level sampled by the corresponding phyad input upon pow er-up/reset. for example, as figure 5 (left- side) shows, if a given phyad input is resistiv ely pulled high then the corresponding output will be configured as an active low driver . on the right side, we can see that if a given phyad input is resistively pulled low then the corresponding output wi ll be configured as an active high driver. the phy address configuration pins should not be connected to gnd or vcc directly, but must be pulled high or low through a resistor (ex 5.1k ? ). if no led indications are neede d, the components of the led path (led+510 ? ) can be removed. pad[0:4]/ led[0:4] pad[0:4]/ led[0:4] vcc led 510 ohm 5.1k ohm led 5.1k ohm 510 ohm phy address[:] = logical 1 phy address[:] = logical 0 led indication = active low led indication = active high figure 5. led and phy address configuration table 27. led definitions led led definitions led0 link led1 full duplex led2 [cl led mode]10-activity led3 [cl led mode]fiber/100-activity led4 collision www..net
RTL8201CL datasheet single-chip/port 10/100 fast ethernet ph yceiver 20 track id: jatr-1076-21 rev. 1.24 7.6. serial network interface the RTL8201CL also supports the traditional 7-wire seri al interface to operate with legacy macs or embedded systems. to setup for this mode of oper ation, pull the mii/snib pi n low. by doing so, the RTL8201CL will ignore the setup of the ane and speed pins. in th is mode, the RTL8201CL will set the default operation to 10m bps and half-duplex mode. note: the RTL8201CL also supports full-duplex mode operation if the du plex pin has been pulled high. this interface consists of a 10mbps transmit and receive clock generated by phy, 10mbps transmit and receive serial data, transmit enable, coll ision detect, and carry sense signals. 7.7. power down, link down, power saving, and isolation modes the RTL8201CL offers four types of power saving mode operation. this section describes how to implement each mode. the first three modes are conf igured through software, and the fourth through hardware. table 28. power saving mode pin settings mode description analog off setting bit 11 of register 17 to 1 will put the RTL8201CL into analog off state. in analog off state, the RTL8201CL will power down all analog functions such as transmit, receive, pll, etc. however, the internal 25mhz crystal oscillator will not be po wered down. digital functions in this mode are still available, which allows r eacquisition of analog functions ldps setting bit 12 of register 17 to 1, or pulling the ldps pin high will put the RTL8201CL into ldps (link down power saving) mode. in ldps mode, the RTL8201CL will detect the link status to decide whether or not to turn off the transmit function. if the link is off, flp or 100mbps idle/10mbps nlp will not be transmitted. howe ver, some signals similar to nlp will be transmitted. once the receiver detects leveled si gnals, it will stop the signal and transmit flp or 100mbps idle/10mbps nlp again. this can cut power used by 60%~80% when the link is down. pwd setting bit 11 of register 0 to 1 puts the rtl8 201cl into power down mode. this is the maximum power saving mode while the RTL8201CL is still alive. in pwd mode, the RTL8201CL will turn off all analog/digital functions except the mdc/md io management interface. therefore, if the RTL8201CL is put into pwd mode and the mac wants to recall the phy, it must create the mdc/mdio timing by itself (this is done by software). isolation this mode is different from the three previous software configured power saving modes. this mode is configured by hardware pin 43. setting pin 43 high will isolate the RTL8201CL from the media access controller (mac) and the mdc/mdio management interface. in this mode, power consumption is minimal. 7.8. media interface 7.8.1. 100base-tx 100base-tx transmit function transmit data in 4-bit nibbles (txd[3:0]) clocked at 25mhz (txc) is transformed into 5b symbol code (4b/5b encoding). scrambling, seri alizing, and conversion to 125mhz, and nrz to nrzi then takes place. after this process, the nrzi signal is passed to the mlt-3 encoder, then to the transmit line driver. www..net
RTL8201CL datasheet single-chip/port 10/100 fast ethernet ph yceiver 21 track id: jatr-1076-21 rev. 1.24 the transmitter will first assert txen. before transm itting the data pattern, it will send a /j/k/ symbol (start-of-frame delimiter), the data symbol, and finally a /t/r/ symbol known as the end-of-frame delimiter. the 4b/5b and the scramble process can be bypassed via a phy register setting (see table 1, page 4, pin number 24). for better emi performance, the seed of the scrambler is based on the phy address. in a hub/switch environment, each rtl 8201cl will have different scrambler seeds and so spread the output of the mlt-3 signals. 100base-tx receive function the received signal is compensated by the adaptive eq ualizer to make up for signal loss due to cable attenuation and inter symbol interference (isi). ba seline wander correction mo nitors the process and dynamically applies corrections to th e process of signal equa lization. the pll then recovers the timing information from the signals and from the receive clock. with this, the received signal is sampled to form nrzi data. the next steps are the nr zi to nrz process, unscrambling of the data, serial to parallel and 5b to 4b conversion, and passing of the 4b nibble to the mii interface. 7.8.2. 100base-fx fiber mode operation the RTL8201CL can be configured as 100base-fx via hardware configuration. the hardware 100base-fx setting takes priority over nway settings. a scrambler is not required in 100base-fx. 100base-fx transmit function di-bits of txd are processed as 100base-tx except wi thout a scrambler before the nrzi stage. instead of converting to mlt-3 signals, as in 100base-tx, the serial data stream is driven out as nrzi pecl signals, which enter the fiber transc eiver in differential-pairs form. 100base-fx receive function the signal is received through pecl receiver inputs from the fiber transceiver and directly passed to the clock recovery circuit for data/clock recovery. th e scrambler/de-scrambler is bypassed in 100base-fx. 7.8.3. 10base-t tx/rx 10base-t transmit function transmit data in 4-bit nibbles (txd[ 3:0]) clocked at 2.5mhz (txc) is fi rst fed to a parallel-to-serial converter, then the 10mbps nrz si gnal is sent to a manchester en coder. the manchester encoder converts the 10mbps nrz data into a manchester enc oded data stream for the tp transmitter and adds a start of idle pulse (soi) at the end of the packet as specified in ieee 802.3. fi nally, the encoded data stream is shaped by a bandlimited filter embedded in the RTL8201CL and then transmitted. 10base-t receive function in 10base-t receive mode, the manchester decoder in the RTL8201CL converts the manchester encoded data stream into nrz data by decoding the data and st ripping off the soi pulse. th en the serial nrz data stream is converted to a parallel 4-bit nibble signal (rxd[0:3]). www..net
RTL8201CL datasheet single-chip/port 10/100 fast ethernet ph yceiver 22 track id: jatr-1076-21 rev. 1.24 7.9. repeater mode operation setting bit 15 of register 17 to 1, or pulling the rptr pin high, sets the RTL8201CL into repeater mode. in repeater mode, the RTL8201CL w ill assert crs high only when receiving a pack et. in nic mode, the RTL8201CL will assert crs high both when transmitting and receiving packets. if using the RTL8201CL in a nic or switch application, set to th e default mode. nic/switch mode is the default setting and has the rptr pin pulled low, or bit 15 of register 17 is set to 0. 7.10. reset, and transmit bias the RTL8201CL can be reset by pulling the resetb pin low for about 10ms, then pulling the pin high. it can also be reset by setting bit 15 of register 0 to 1, and then setting it back to 0. reset will clear the registers and re-initialize them. the media in terface will disconnect and restart the auto- negotiation/parallel detection process. the rtset pin must be pulled low by a 2k ? resister with 1% accuracy to establish an accurate transmit bias. this will affect the signal qua lity of the transmit waveform. keep its circuitry away from other clock traces and transmit/receive paths to avoid signal interference. 7.11. 3.3v power supply and voltage conversion circuit the RTL8201CL is fabricated in a 0.18 m process. the core circuit needs to be powered by 1.8v, however, the digital io and dac ci rcuits need a 3.3v power supply. a regulator is embedded in the RTL8201CL to convert 3.3v to 1.8v. as with many commercial voltage c onversion devices, the 1.8v output pin (pwfbout) of this circu it requires the use of an output capacitor (22uf tantalum capacitor) as part of the device frequency compensation, a nd another small capacitor (0.1uf) for high frequency noise de-coupling. pwfbin is fed with the 1.8v powe r from pwfbout through a ferrite bead as shown in the reference design schematic document (available for download from www.realtek.com.tw). note: do not supply 1.8v produced by any pow er device other than pwfbout and pwfbin. the analog and digital ground planes should be as large and intact as possible. if the ground plane is large enough, the analog and digital grounds can be separated, which is the ideal configuration. however, if the total ground plane is not sufficiently large, partition of the ground plan e is not a good idea. in this case, all the ground pins can be connected together to a larger single and intact ground plane. 7.12. far end fault indication the mii reg.1.4 (remote fault) is the far end fault indication (fefi) bit when 100fx mode is enabled and indicates when a fefi has been detected. fefi is an alternativ e in-band signaling method which is composed of 84 consecutive ?1?s followed by one ?0 ?. when the RTL8201CL det ects this pattern three times, reg.1.4 is set, which means the transmit path (t he remote side?s receiv e path) has a problem. on the other hand, if an incoming signal fails to cause a ?link ok?, the RTL8201CL will start sending this pattern, which in turn causes the remote side to detect a far end fault. this means that the receive path has a problem from the point of view of the RTL8201CL. the fe fi mechanism is used only in 100base-fx mode. www..net
RTL8201CL datasheet single-chip/port 10/100 fast ethernet ph yceiver 23 track id: jatr-1076-21 rev. 1.24 8. characteristics 8.1. dc characteristics 8.1.1. absolute maximum ratings table 29. absolute maximum ratings item minimum typical maximum supply voltage 3.0v 3.3v 3.6v storage temperature -55 c 125 c 8.1.2. operating conditions table 30. operating conditions item conditions minimum typical maximum vcc 3.3v 3.3v supply voltage 3.0v 3.3v 3.6v ta operating temperature 0 c 70 c 8.1.3. power dissipation test condition: vcc=3.3v table 31. power dissipation symbol condition total current consumption p ldps link down power saving mode 19ma p anaoff analog off mode 19ma p pwd power down mode 14ma p isolate isolate mode 14ma p 100f 100base full duplex 116ma p 10f 10base-t full duplex 120ma p 10tx 10base-t transmit 120ma p 10rx 10base-t receive 19ma p 10idle 10base-t idle 18ma 8.1.4. input voltage: vcc table 32. input voltage: vcc symbol condition minimum maximum ttl v ih input high vol. 0.5*vcc vcc +0.5v ttl v il input low vol. -0.5v 0.3*vcc ttl v oh output high vol. ioh=-8ma 0.65*vcc vcc ttl v ol output low vol. iol=8ma 0.3*vcc ttl i oz tri-state leakage vout=vcc or gnd -110ua 10ua i in input current vin=vcc or gnd -1ua 10ua i pl input current with internal weak pull low resistor vin=vcc or gnd -1ua 100ua i ph input current with internal weak pull high resistor vin=vcc or gnd -110ua 10ua www..net
RTL8201CL datasheet single-chip/port 10/100 fast ethernet ph yceiver 24 track id: jatr-1076-21 rev. 1.24 symbol condition minimum maximum pecl v ih pecl input high vol. vdd -1.16v vdd -0.88v pecl v il pecl input low vol. vdd -1.81v vdd -1.47v pecl v oh pecl output high vol. vdd -1.02v pecl v ol pecl output low vol. vdd -1.62v 8.2. ac characteristics 8.2.1. mii transmission cycle timing table 33. mii transmission cycle timing symbol description minimum typical maximum unit 100mbps 14 20 26 ns t 1 txclk high pulse width 10mbps 140 200 260 ns 100mbps 14 20 26 ns t 2 txclk low pulse width 10mbps 140 200 260 ns 100mbps 40 ns t 3 txclk period 10mbps 400 ns 100mbps 10 24 ns t 4 txen, txd[0:3] setup to txclk rising edge 10mbps 5 ns 100mbps 10 25 ns t 5 txen, txd[0:3] hold after txclk rising edge 10mbps 5 ns 100mbps 40 ns t 6 txen sampled to crs high 10mbps 400 ns 100mbps 160 ns t 7 txen sampled to crs low 10mbps 2000 ns 100mbps 60 70 140 ns t 8 transmit latency 10mbps 2000 ns 100mbps 100 170 ns t 9 sampled txen inactive to end of frame 10mbps ns figure 6 shows an example of a packet tran sfer from mac to phy on the mii interface. txclk v i h(min) v il(max) txd[0:3] txen v ih(min) v il(max) t 4 t 5 t 3 t 1 t 2 figure 6. mii transmission cycle timing-1 www..net
RTL8201CL datasheet single-chip/port 10/100 fast ethernet ph yceiver 25 track id: jatr-1076-21 rev. 1.24 txclk txen txd[0:3] crs tptx+- t 6 t 8 t t 9 7 figure 7. mii transmission cycle timing-2 8.2.2. mii reception cycle timing table 34. mii reception cycle timing symbol description minimum typical maximum unit 100mbps 14 20 26 ns t 1 rxclk high pulse width 10mbps 140 200 260 ns 100mbps 14 20 26 ns t 2 rxclk low pulse width 10mbps 140 200 260 ns 100mbps 40 ns t 3 rxclk period 10mbps 400 ns 100mbps 10 ns t 4 rxer, rxdv, rxd[0:3] setup to rxclk rising edge 10mbps 6 ns 100mbps 10 ns t 5 rxer, rxdv, rxd[0:3] hold after rxclk rising edge 10mbps 6 ns 100mbps 130 ns t 6 receive frame to crs high 10mbps 2000 ns 100mbps 240 ns t 7 end of receive frame to crs low 10mbps 1000 ns 100mbps 150 ns t 8 receive frame to sampled edge of rxdv 10mbps 3200 ns 100mbps 120 ns t 9 end of receive frame to sampled edge of rxdv 10mbps 1000 ns www..net
RTL8201CL datasheet single-chip/port 10/100 fast ethernet ph yceiver 26 track id: jatr-1076-21 rev. 1.24 figure 8 shows an example of a packet tran sfer from phy to mac on the mii interface. rxclk rxd[0:3] rxdv rxer v ih(min) v i l(max) v ih(min) v i l(max) t 4 t 5 t 1 t 3 t 2 figure 8. mii reception cycle timing-1 rxclk rxdv rxd[0:3] crs tprx+- t 8 t 6 t 7 t 9 figure 9. mii reception cycle timing-2 www..net
RTL8201CL datasheet single-chip/port 10/100 fast ethernet ph yceiver 27 track id: jatr-1076-21 rev. 1.24 8.2.3. sni transmission cycle timing table 35. sni transmission cycle timing symbol description minimum maximum unit t 1 txclk high pulse width 36 ns t 2 txclk low pulse width 36 ns t 3 txclk period 80 120 ns t 4 txen, txd0 setup to txclk rising edge 20 ns t 5 txen, txd0 hold after txclk rising edge 10 ns t 8 transmit latency 50 ns figure 10 shows an example of a packet transf er from mac to phy on the sni interface. note: sni mode only runs at 10mbps. txclk v ih(min) v il(max) t 1 t 3 t 2 txd0 txen v ih(min) v il(max) t 4 t 5 figure 10. sni transmission cycle timing-1 txclk txen txd0 tptx+- t 8 t 9 figure 11. sni transmission cycle timing-2 www..net
RTL8201CL datasheet single-chip/port 10/100 fast ethernet ph yceiver 28 track id: jatr-1076-21 rev. 1.24 8.2.4. sni reception cycle timing table 36. sni reception cycle timing symbol description minimum typical maximum unit t 1 rxclk high pulse width 36 ns t 2 rxclk low pulse width 36 ns t 3 rxclk period 80 120 ns t 4 rxd0 setup to rxclk rising edge 40 ns t 5 rxd0 hold after rxclk rising edge 40 ns t 6 receive frame to crs high 50 ns t 7 end of receive frame to crs low 160 ns t 8 decoder acquisition time 600 1800 ns figure 12 shows an example of a packet transf er from phy to mac on the sni interface. note: sni mode only runs at 10mbps. rxclk rxd0 v ih(min) v il(max) v ih(min) v il(max) t 4 t 5 t 1 t 3 t 2 figure 12. sni reception cycle timing-1 rxclk rxd0 crs tprx+- t 6 t 8 t 7 figure 13. sni reception cycle timing-2 www..net
RTL8201CL datasheet single-chip/port 10/100 fast ethernet ph yceiver 29 track id: jatr-1076-21 rev. 1.24 8.2.5. mdc/mdio timing table 37. mdc/mdio timing symbol description minimum maximum unit t 1 mdc high pulse width 160 ns t 2 mdc low pulse width 160 ns t 3 mdc period 400 ns t 4 mdio setup to mdc rising edge 10 ns t 5 mdio hold time from mdc rising edge 10 ns t 6 mdio valid from mdc rising edge 0 300 ns mdc mdio sourced by sta v ih(min) v il(max) v ih(min) v il(max) mdio sourced by rtl8201cp v ih(min) v il(max) t 4 t 5 t 3 t 1 t 2 t 6 figure 14. mdc/mdio timing transmission without collision figure 15 shows an example of a pack et transfer from mac to phy. figure 15. mdc/mdio mac to phy transmission without collision www..net
RTL8201CL datasheet single-chip/port 10/100 fast ethernet ph yceiver 30 track id: jatr-1076-21 rev. 1.24 reception without error figure 16 shows an example of a pack et transfer from phy to mac. figure 16. mdc/mdio phy to mac reception without error 8.3. crystal characteristics table 38. crystal characteristics parameter range nominal frequency 25.000mhz oscillation mode base wave frequency tolerance at 25 c 50 ppm operating temperature range -10 c ~ +70 c equivalent series resistance 30 ohm max. drive level 0.1 mv load capacitance 20 pf shunt capacitance 7 pf max. insulation resistance mega ohm min./dc 100v test impedance meter saunders 250a aging rate per year 0.0003% 8.4. transformer characteristics table 39. transformer characteristics parameter transmit end receive end turn ratio 1:1 ct 1:1 inductance (min.) 350 uh @ 8ma 350 uh @ 8ma www..net
RTL8201CL datasheet single-chip/port 10/100 fast ethernet ph yceiver 31 track id: jatr-1076-21 rev. 1.24 9. mechanical dimensions see the following page for drawing related notes. www..net
RTL8201CL datasheet single-chip/port 10/100 fast ethernet ph yceiver 32 track id: jatr-1076-21 rev. 1.24 9.1. mechanical dimensions notes notes: 1.to be determined at seating plane -c- 2.dimensions d1 and e1 do not include mold protrusion. symbol dimension in inchs dimension in millimeters d1 and e1 are maximum plastic body size dimensions including mold mismatch. min nom max min nom max 3.dimension b does not include dambar protrusion. a - - 0.067 - - 1.70 dambar can not be located on the lower radius of the foot. a1 0.000 0.004 0.008 0.00 0. 1 0.20 4.exact shape of each corner is optional. a2 0.051 0.055 0.059 1.30 1.40 1.50 5.these dimensions apply to the flat section of the lead b 0.006 0.009 0.011 15 0.22 0.29 between 0.10 mm and 0.25 mm from the lead tip. b1 0.006 0.008 0.010 0.15 0.20 0.25 6. a1 is defined as the distance from the seating plane to the lowest point of the package body. c1 0.004 - 0.006 0.09 - 0.16 7.controlling dimension: millimeter. d 0.354 bsc 9.00 bsc 8. reference document: jedec ms-026, bbc d1 0.276 bsc 7.00 bsc e 0.354 bsc 9.00 bsc title: 48ld lqfp (7x7x1.4mm) e1 0.276 bsc 7.00 bsc package outline drawing, footprint 2.0mm e 0.020 bsc 0.50 bsc leadframe material: l 0.016 0.024 0.031 0.40 0.60 0.80 doc. no. l1 0.039 ref 1.00 ref version 1 0 3.5 9 0 3.5 9 approve page of 1 0 - - 0 - - dwg no. ss048 - p1 2 12 typ 12 typ check date 3 12 typ 12 typ realtek semiconductor corp. www..net
RTL8201CL datasheet single-chip/port 10/100 fast ethernet ph yceiver 33 track id: jatr-1076-21 rev. 1.24 10. ordering information table 40. ordering information part number package status RTL8201CL rev. c. 48-pin lqfp RTL8201CL-lf rev. c. 48-pin lqfp lead (pb)-free package RTL8201CL-vd rev. d. 48-pin lqfp RTL8201CL-vd-lf rev. d. 48-pin lqfp lead (pb)-free package note: see page 3 for lead (pb)-free package identification. realtek semiconductor corp. headquarters no. 2, innovation road ii hsinchu science park, hsinchu 300, taiwan tel.: +886-3-578-0211. fax: +886-3-557-6047 www.realtek.com.tw www..net

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